Schematic Address Counter (AC) of LCD | Controller Circuit

Friday, December 2, 2011

Schematic Address Counter (AC) of LCD

3.1.3 Address Counter (AC)
address counter ( ′adres ′kau̇ntər ) ( computer science ) A counter which increments an initial memory address as a block of data is being transferred.

The address counter (AC) assigns addresses to both DDRAM and CGRAM. When an address of an instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by the instruction.
After writing into (reading from) DDRAM or CGRAM, the AC is automatically incremented by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/W = 1.
3.1.4 Initializing by Internal Reset Circuit

We have used an LCD (liquid crystal display). They are all around us -- in laptop computers, digital clocks and watches, microwave ovens, CD players and many other electronic devices. LCDs are common because they offer some real advantages over other display technologies. They are thinner and lighter and draw much less power than cathode ray tubes (CRTs), An internal reset circuit automatically initializes theHD44780 when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 10 ms after VCC rises to 4.5 V.
3.1.5 Pin Assighnment

The pin assignment shown in Table . is the industry standard for character LCD-modules with a maximum of 80 characters.
Pin number Symbol Level I/O Function


1 Vss - - Power supply (GND)

2 Vcc - - Power supply (+5V)

3 Vee - - Contrast adjust

4 RS 0/1 I 0 = Instruction input

1 = Data input

5 R/W 0/1 I 0 = Write to LCD module

1 = Read from LCD module

6 E 1, 1->0 I Enable signal

7 DB0 0/1 I/O Data bus line 0 (LSB)

8 DB1 0/1 I/O Data bus line 1

9 DB2 0/1 I/O Data bus line 2

10 DB3 0/1 I/O Data bus line 3

11 DB4 0/1 I/O Data bus line 4

12 DB5 0/1 I/O Data bus line 5

13 DB6 0/1 I/O Data bus line 6

14 DB7 0/1 I/O Data bus line 7 (MSB)

Clear display 0 0 0 0 0 0 0 0 0 1 Clears display and returns cursor to the home position (address 0). 1.64mS


Cursor home 0 0 0 0 0 0 0 0 1 * Returns cursor to home position (address 0). Also returns display being shifted to the original position. DDRAM contents remains unchanged. 1.64mS

Write to CGRAM or DDRAM 1 0 write data Writes data to CGRAM or DDRAM. 40uS

Read from CGRAM or DDRAM 1 1 read data Reads data from CGRAM or DDRAM. 40uS




 BACK to Content Page

 . Next Page

 .   Previous Page
tags:- ′adres ′kau̇ntər ,Sample Address Counter ,Program counter ,The program counter, or PC (also called the instruction pointer to a seminal Intel instruction set, such as the 8080 or 4004, or instruction address ,HEX address counter,8051-Assembler,Addresses and Counter-Motions ,Address Counter (AC),“Set DD RAM Address”,Advanced Microprocessors And Peripherals ,auto address increment counter,DDRAM Display data RAM CGRAM Character generator RAM ACC CG RAM address ADD DD RAM address, corresponds to cursor address AC Address counter Program counter address

No comments:

Post a Comment