The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families.
Some features of octal D-type Flip-Flop with 3-State Output
• Eight Latches in a Single Package.
• 3-State Outputs for Bus Interfacing.
• Hysteresis on Latch Enable.
• Edge-Triggered D-Type Inputs.
• Buffered Positive Edge-Triggered Clock.
• Hysteresis on Clock Input to Improve Noise Margin.
• Input Clamp Diodes Limit High Speed Termination Effects
BACK to Content Page
.
Next Page
.
Previous Page
used urological ultrasound with transrectal probe cyprus circuit diagram of piezoelectric sensor based heart beat monitor 16f877a frequency counter software free download c language microcontroller projects in c for 8051 full discription with circuit diagram max232 atmel programator rs232
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families.
Some features of octal D-type Flip-Flop with 3-State Output
• Eight Latches in a Single Package.
• 3-State Outputs for Bus Interfacing.
• Hysteresis on Latch Enable.
• Edge-Triggered D-Type Inputs.
• Buffered Positive Edge-Triggered Clock.
• Hysteresis on Clock Input to Improve Noise Margin.
• Input Clamp Diodes Limit High Speed Termination Effects
BACK to Content Page
.
Next Page
.
Previous Page
used urological ultrasound with transrectal probe cyprus circuit diagram of piezoelectric sensor based heart beat monitor 16f877a frequency counter software free download c language microcontroller projects in c for 8051 full discription with circuit diagram max232 atmel programator rs232
Posts
No comments:
Post a Comment