Testing Circuit
To test our circuit, connect various voltages to pin 6 of the ADC0804. we have connected a jumper from pin 6 to 5 volts, the voltage on the sample program should say 5 volts. Remove the jumper. Try connecting a 2.2k resistor from pin 6 to ground and another 2.2k resistor from pin 6 to 5 volts. The result should be around 2.5 volts. Remove the resistors.
Try playing with the 220 uF capacitor and the 15k Ohm resistor. Connect the negative leg of the capacitor to ground and the positive leg to pin 6 of the ADC0804. Connect the resistor from pin 6 to 5 volts. The voltage should rise quickly and then slower as it approaches 5 volts. Now remove the resistor. The voltage should stay at the same voltage and slowly decay as the capacitor loses its charge. Connect the resistor from pin 6 to ground to quickly discharge the capacitor.
designed to address the real life issues associated with
testing A/D converters. The skills and knowledge acquired in this course extend well beyond A/D
converters to provide a functional model for testing a variety of mixed signal circuits.
Today many Test, Product, and Applications Engineers are familiar with digital circuits but lack
experience with mixed signal devices and modern mixed signal ATE equipment.
Data Converters
• Practical aspects of converter testing
• Signal source
• Filters for signal source harmonic distortion attenuation
• Clock generator requirements
• Evaluation board considerations
• D/A converter design
Clock Generator
• Let us check if for the clock a "valuepriced" signal generator will suffice...
• No! The clock signal controls sampling instants – which we assumed to be precisely equi-distant in time (period T)
• Variability in T causes errors
– "Aperture Uncertainty" or "Aperture Jitter"
• How much Jitter can we tolerate?
Once we have a good enough generator, other circuit and test setup related issues may determine jitter, but...
• Usually, clock jitter in the single-digit pico-second range can be prevented by appropriate design techniques
– Separate supplies
– Separate analog and digital clocks
– Short inverter chains between clock source and destination
• Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter:
– RMS noise proportional to input frequency
– RMS noise proportional to input amplitude
àIn cases where clock jitter limits the dynamic range, it’s easy to tell, but may be difficult to fix...
Evaluation Board
• Planning begins with converter pin-out
– Example of poor pin-outà clock pin right next to a digital output...
• Not "Black Magic", but weeks of design time and studying
• Key aspects
– Supply/ground routing, bypass capacitors
– Coupling between signals
• Good idea to look at ADC vendor datasheets for example layouts/schematics/application
notes
How to Get the Bits Off Chip?
• "Full swing" CMOS signaling works well for
fCLK<100MHz- For higher frequencies: – Uncontrolled characteristic impedance – High swingà higher level of spurious coupling to other signals – Low power efficiency • But we want to build faster ADCs... • Alternative to CMOS: LVDS – Low Voltage Differential Signaling • LVDS vs. CMOS: – Higher speed, more power efficient at high speed – Two pins/bit! State-of-the-art converters almost always yield surprises in silicon – If models anticipate everything, the application probably isn’t state-of-the-art • Analog designers and mixed-signal architects at times invent new circuits while measuring in the lab • How do we debug converters? – Start with a simple time domain test. Does the captured digital waveform look like a sine wave? – Begin your DFT/INL signature analysis by scaling down sampling frequencies and signal input frequencies together – If you can’t explain performance with essentially infinite settling times, don’t add dynamic errors to the mix. Typical problems come from nonidealities never built into your "model" – E.g. half-circuit models for fully-differential circuits inherently can’t explain some types of differential-symmetry errors • You can’t afford to rediscover old nonidealities in new silicon – Talking to veterans early in the modeling phase can be important Design teams usually track down and fix single-cause problems quickly • Problems due to circuit interactions are much more difficult to debug, try to avoid by good design/layout • Interaction examples: – Digital activity-dependent clock jitter • S/(N+D) degradation only happens when large amplitude, high frequency analog inputs coincide with the offending digital activity – Distortion cancellation • Nonlinear phenomena don’t obey superposition Never assume all of your data is good – One bad data set can “rule out” the correct explanation, leading you astray forever • "Compare measurements to themselves“ • But, noise is a random variable, and the noise power in 1000 time samples will vary from DFT to DFT • How big an effect is this? DAC architecture has significant impact on DNL • INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision • Results are for uncorrelated random element variations • Systematic errors and correlations are usually also important Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9. This is Testing Circuit of humidity sensing project.
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To test our circuit, connect various voltages to pin 6 of the ADC0804. we have connected a jumper from pin 6 to 5 volts, the voltage on the sample program should say 5 volts. Remove the jumper. Try connecting a 2.2k resistor from pin 6 to ground and another 2.2k resistor from pin 6 to 5 volts. The result should be around 2.5 volts. Remove the resistors.
Try playing with the 220 uF capacitor and the 15k Ohm resistor. Connect the negative leg of the capacitor to ground and the positive leg to pin 6 of the ADC0804. Connect the resistor from pin 6 to 5 volts. The voltage should rise quickly and then slower as it approaches 5 volts. Now remove the resistor. The voltage should stay at the same voltage and slowly decay as the capacitor loses its charge. Connect the resistor from pin 6 to ground to quickly discharge the capacitor.
designed to address the real life issues associated with
testing A/D converters. The skills and knowledge acquired in this course extend well beyond A/D
converters to provide a functional model for testing a variety of mixed signal circuits.
Today many Test, Product, and Applications Engineers are familiar with digital circuits but lack
experience with mixed signal devices and modern mixed signal ATE equipment.
Data Converters
• Practical aspects of converter testing
• Signal source
• Filters for signal source harmonic distortion attenuation
• Clock generator requirements
• Evaluation board considerations
• D/A converter design
Clock Generator
• Let us check if for the clock a "valuepriced" signal generator will suffice...
• No! The clock signal controls sampling instants – which we assumed to be precisely equi-distant in time (period T)
• Variability in T causes errors
– "Aperture Uncertainty" or "Aperture Jitter"
• How much Jitter can we tolerate?
Once we have a good enough generator, other circuit and test setup related issues may determine jitter, but...
• Usually, clock jitter in the single-digit pico-second range can be prevented by appropriate design techniques
– Separate supplies
– Separate analog and digital clocks
– Short inverter chains between clock source and destination
• Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter:
– RMS noise proportional to input frequency
– RMS noise proportional to input amplitude
àIn cases where clock jitter limits the dynamic range, it’s easy to tell, but may be difficult to fix...
Evaluation Board
• Planning begins with converter pin-out
– Example of poor pin-outà clock pin right next to a digital output...
• Not "Black Magic", but weeks of design time and studying
• Key aspects
– Supply/ground routing, bypass capacitors
– Coupling between signals
• Good idea to look at ADC vendor datasheets for example layouts/schematics/application
notes
How to Get the Bits Off Chip?
• "Full swing" CMOS signaling works well for
fCLK<100MHz- For higher frequencies: – Uncontrolled characteristic impedance – High swingà higher level of spurious coupling to other signals – Low power efficiency • But we want to build faster ADCs... • Alternative to CMOS: LVDS – Low Voltage Differential Signaling • LVDS vs. CMOS: – Higher speed, more power efficient at high speed – Two pins/bit! State-of-the-art converters almost always yield surprises in silicon – If models anticipate everything, the application probably isn’t state-of-the-art • Analog designers and mixed-signal architects at times invent new circuits while measuring in the lab • How do we debug converters? – Start with a simple time domain test. Does the captured digital waveform look like a sine wave? – Begin your DFT/INL signature analysis by scaling down sampling frequencies and signal input frequencies together – If you can’t explain performance with essentially infinite settling times, don’t add dynamic errors to the mix. Typical problems come from nonidealities never built into your "model" – E.g. half-circuit models for fully-differential circuits inherently can’t explain some types of differential-symmetry errors • You can’t afford to rediscover old nonidealities in new silicon – Talking to veterans early in the modeling phase can be important Design teams usually track down and fix single-cause problems quickly • Problems due to circuit interactions are much more difficult to debug, try to avoid by good design/layout • Interaction examples: – Digital activity-dependent clock jitter • S/(N+D) degradation only happens when large amplitude, high frequency analog inputs coincide with the offending digital activity – Distortion cancellation • Nonlinear phenomena don’t obey superposition Never assume all of your data is good – One bad data set can “rule out” the correct explanation, leading you astray forever • "Compare measurements to themselves“ • But, noise is a random variable, and the noise power in 1000 time samples will vary from DFT to DFT • How big an effect is this? DAC architecture has significant impact on DNL • INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision • Results are for uncorrelated random element variations • Systematic errors and correlations are usually also important Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9. This is Testing Circuit of humidity sensing project.
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. Next Page
. Previous Page
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