The PIC microcontrollers have multiple General Purpose I/O (GPIO) pins, and can be easily configured to implement Maxim/Dallas Semiconductor’s 1-Wire protocol. The 1-Wire protocol allows interaction with many Maxim/Dallas Semiconductor parts, including battery and thermal management devices, memory, I Button, etc. 1-Wire devices provide solutions for identification, memory, timekeeping, measurement and control. The 1-Wire data interface is reduced to the absolute minimum (single data line with a ground reference). As most 1-Wire devices provide a relatively small amount of data, the typical data rate of 16 kbps is sufficient for the intended tasks. It is often convenient to use a GPIO pin of an 8-bit or 16-bit microcontroller in a “bit banging” manner to act as the bus master. 1-Wire devices communicate using a single data line and well-defined, time tested protocols.
1 Wire interface circuit is show with this figure;
Operations of the 1-Wire BUS
The four basic operations of a 1-Wire bus are Reset, Write 0 bit, Write 1 bit and Read bit. Using these bit operations, one has to derive a byte or a frame of bytes. The bus master initiates and controls all of the 1-Wire communication. Figure 2 illustrates the 1-Wire communication timing diagram. It is similar to Pulse Width Modulation (PWM) because, the data is transmitted by wide (logic ‘0’) and narrow (logic ‘1’) pulse widths during data bit time periods or time slots. The timing diagram also contains the recommended time values for robust communication across various line conditions.
A communication sequence starts when the bus master drives a defined length “Reset” pulse that synchronizes the entire bus. Every slave responds to the “Reset” pulse with a logic-low “Presence” pulse. To write the data, the master first initiates a time slot by driving the 1-Wire line low, and then, either holds the line low (wide pulse) to transmit a logic ‘0’ or releases the line (short pulse) to allow the bus to return to the logic ‘1’ state. To read the data, the master again initiates a time slot by driving the line with a narrow low pulse. A slave can then either return a logic ‘0’ by turning on its open-drain output and holding the line low to extend the pulse, or return a logic ‘1’ by leaving its open-drain output off to allow the line to recover.
Source; Microchip
1 Wire interface circuit is show with this figure;
Operations of the 1-Wire BUS
The four basic operations of a 1-Wire bus are Reset, Write 0 bit, Write 1 bit and Read bit. Using these bit operations, one has to derive a byte or a frame of bytes. The bus master initiates and controls all of the 1-Wire communication. Figure 2 illustrates the 1-Wire communication timing diagram. It is similar to Pulse Width Modulation (PWM) because, the data is transmitted by wide (logic ‘0’) and narrow (logic ‘1’) pulse widths during data bit time periods or time slots. The timing diagram also contains the recommended time values for robust communication across various line conditions.
A communication sequence starts when the bus master drives a defined length “Reset” pulse that synchronizes the entire bus. Every slave responds to the “Reset” pulse with a logic-low “Presence” pulse. To write the data, the master first initiates a time slot by driving the 1-Wire line low, and then, either holds the line low (wide pulse) to transmit a logic ‘0’ or releases the line (short pulse) to allow the bus to return to the logic ‘1’ state. To read the data, the master again initiates a time slot by driving the line with a narrow low pulse. A slave can then either return a logic ‘0’ by turning on its open-drain output and holding the line low to extend the pulse, or return a logic ‘1’ by leaving its open-drain output off to allow the line to recover.
Source; Microchip
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